The present disclosure is directed to semiconductor devices and, more specifically, to thyristor-based memory that may include a thyristor having a base region implanted with a high ionization energy impurity, such as a dopant.
With the progression of semiconductor technology, semiconductor devices of ever-decreasing geometry have been realized for enabling the fabrication of integrated circuits of increased density and complexity. While this industry, in general, may be understood to address a variety of different types of circuits; the design, construction and manufacture of semiconductor memory devices—which may be used for storage of digital data—has conventionally been of particular interest to particular segments of the industry.
Most semiconductor memory devices may be described as static random access memory (SRAM) or dynamic random access memory (DRAM). SRAM's, conventionally, have been used for applications requiring quick performance and responsiveness. Quick responsiveness may be understood to enable ready availability—i.e., access speed.
In contrast, DRAM's typically have been associated with applications of reduced speed requirements. These DRAM's, although of responsiveness slower than conventional SRAM's might still have found favor by way of their density advantage—i.e., area per bit.
More recently, however, thyristors have been introduced as a type of Negative Differential Resistance (NDR) SRAM device that may offer speed potential as well as density. Additionally, some of the more recent thyristor-based memory may be capable of realization via readily available CMOS processes, procedures and equipment.
One consideration associated with design of thyristor-based memory concerns the magnitude of a thyristor's holding current—i.e., the current necessary for the device to preserve a conductive state (on-state). If such thyristor is operable with a low holding current, low power dissipation may be achieved during the overall operation of the memory device. However, these minimum current levels may depend on the desired reliability (e.g., maximum tolerable error density) and noise immunity.
The noise immunity of a thyristor-based memory cell may be related to its blocking characteristics. If the gain of the thyristor is too great, then the threshold level of the thyristor's blocking state may drop to a level that may hinder data preservation. An excessive gain may cause the thyristor to be vulnerable to noise influences, wherein the noise may erroneously trigger the thyristor from a non-conductive state to a conductive state. For similar reasons, it may be difficult to transition a thyristor of excessive gain from a conductive state to a non-conductive state.
Accordingly, a compromise may be evident when selecting a gain for the constituent bipolar devices of the thyristor element of a thyristor-based memory. The selection of a gain too low for the bipolar devices of the thyristor may hinder the ability to write and preserve data of a first type (conductive state) within the thyristor. On the other hand, the selection of a gain too great may, alternatively, hinder the ability to write and preserve data of second type (non-conductive state). Ideally, the thyristor may be designed with a bipolar gain selected for permitting reliable writing and storage of either of first-type or second-type data, and capable of reliable fabrication over given variance that may affect the gain.
However, various environmental conditions such as temperature may be understood to influence the performance of semiconductor devices. Additionally, during manufacture of thyristor-based semiconductor memory, various processes—e.g., doping, implant, activation, anneal procedures, and the like—may include tolerance levels or limitations that may contribute to device variations; and, likewise, the reliability of the thyristor-based memory to handle data with immunity to noise, environmental influences and temperature variation.